Task 4-1: Build the Brainless Central Processing Unit
Include a picture of your Logisim Brainless Central Processing Unit circuit here:
Figure 1. Brainless Central Processing Unit JCC
Task 4-2: Test and Control the Brainless Central Processing Unit
Perform the testing procedures outlined in the laboratory manual and fill in the blanks below. (Note that these questions appear in the text of the laboratory manual.)
· Record the first number placed on the data bus here: 5
· What do the following three switches need to be set to in order to perform the pass-through operation? /~A_Only = 0 /~Invert= 1 Logic/~Arith= 0
· Enter the second number you entered into the data bus here: 2
· What do the following three switches need to be set to in order to perform the ADD operation? /~A_Only = 1 /~Invert= 1 Logic/~Arith= 0
· Write down the number that appears in the accumulator here: 7
Describe other numerical additions and other operations you checked in order to verify your brainless CPU here: I repeated the additions several times using 3, 4 and 1 and toggled through several times till I got the correct addition.
After you are convinced your circuit is working properly, remove the 4-bit binary keyboard and set the ACC to Data Bus pin to 1. Did the output of the accumulator appear on the data bus? Yes.
How does the output of the ALU change? It changed to Hex E.
If the 4-bit binary keyboard was not removed and the ACC to Data Bus switch is set to 1, what would you expect to see displayed in the hex digit display attached to the data bus?
I expect to see whatever is supplied to the data bus in hex display.
Add the 4-bit binary keyboard back into your circuit and observe the hex digit display on the data bus for various keyboard values. Is the value on the hex digit display what you expected? Yes.
Explain Only 1 signal is being allowed to enter the buffer at a time. Therefore, the buffer is receiving only the output of the register.
Why do you think the register at the output of the ALU is called the ‘accumulator’? Because it stores data that passes through the ALU, it provides a feedback path tho the B input of the ALU and because it can store intermediate arithmetic or logic results.
Task 4-3: Build the Addressing Logic
Include a picture of your Logisim addressing logic circuit here:
Figure 2. Addressing Logic JCC
Test your circuit and record the results in Table 1. Include a picture of your Logisim addressing logic circuit testing set up.
Figure 3. Testing Addressing Logic JCC
Table 1
A
(4-bit binary)
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
0000
1
0
0
0
0
0
0
0
0001
0
0
1
0
0
0
0
0
0010
0
1
0
0
0
0
0
0
0011
0
0
0
1
0
0
0
0
Task 4-4: Build a 4-Bit ROM Memory Cell
Include a picture of your Logisim 4-bit ROM circuit here:
Figure 4. 4-bit ROM memory cell JCC
Test your circuit and record the results in Table 2. Include a picture of your Logisim 4-bit ROM circuit testing set up.
Figure 5. Testing 4-bit ROM memory cell JCC
Table 2
A
(4-bit binary)
Read
Memory Select
Y
(Data Bus)
0001
1
1
1
0101
1
1
5
1000
1
1
8
1000
0
1
X
1000
1
0
X
1000
0
0
X
Task 4-5: Build 4-Bit Output Port
Include a picture of your Logisim 4-bit output port circuit here:
Figure 6. 4-bit output device JCC
Test your circuit and record the results in Table 3.
Table3
Data Bus (4-bit binary)
Write
Memory Select
Q
0001
1
1
1
0010
0
1
Last Q
0011
1
0
Last Q
0011
0
0
Last Q
0011
0
0
0
0011
1
0
0
0011
1
1
3
0001
0
0
0
Task 4-6: Build the 4-Bit RAM Cell
Include a picture of your Logisim 4-bit RAM circuit here:
Figure 7. 4-bit RAM JCC
Test your circuit and record the results in Table 4. Include a picture of your Logisim 4-bit RAM circuit testing set up.
Figure 8. Testing 4-bit RAM JCC
Table4
Data Bus
(4-bit binary)
Write
Memory Select
Read
Q {between register and buffer}
Data Bus {after buffer}
0110
1
1
1
6
6
0110
0
1
1
6
6
0110
1
0
1
6
–
0110
0
0
1
6
–
0110
0
0
0
6
–
0101
1
1
1
5
5
Task 4-7: Build the Brainless Microprocessor
Include a picture of your Logisim brainless microprocessor circuit here:
Task 4-8: Testing and Controlling the Brainless Microprocessor
Follow steps 1 through 3 outlined in the laboratory manual to test your brainless microprocessor circuit. List in Table 5 the control lines you needed to control to store the accumulator (ACC) to
RAM. (If the control line value has no impact, place a dash ‘-‘ in the value column).
Table5
Control line
Value
4-bit binary keyboard
(Address Bus)
Write
0
Read
1
ACC to Data Bus
0
Load ACC
1
/~A_Only
0
/~Invert
0
Logic/~Arith
1
Describe any other tests that you performed. NOTE: the laboratory manual gives you a minimum set of items to test: __________________________________________________________________________
_____________________________________________________________________________________
___________________________________________________________________________________
____________________________________________________________________________________
____________________________________________________________________________________
Table 6 is an example, for the ADD command, of how to fill out tables to record the values of the control lines during every clock cycle.
Table6
Instruction [ Add operand to Accumulator (ACC) ]
Control Line
Value
4-bit Binary Keyboard (Address Bus)
Address of operand
Write
0
Read
1
ACC to Data Bus
0
Load ACC
1
/~A_Only
1
/~Invert
1
Logic/~Arith
0
For all of the instructions you performed (i.e. Subtract, Load ACC, etc.) record the values of the control lines during every clock cycle in Table 7, Table 8and Table 9.
Table7
Instruction [Subtract operand from ACC ]
Control Line
Value
4-bit Binary Keyboard (Address Bus)
3
Write
1
Read
1
ACC to Data Bus
0
Load ACC
1
/~A_Only
1
/~Invert
1
Logic/~Arith
0
Table8
Instruction [Load ACC with operand]
Control Line
Value
4-bit Binary Keyboard (Address Bus)
3
Write
1
Read
1
ACC to Data Bus
1
Load ACC
1
/~A_Only
0
/~Invert
1
Logic/~Arith
1
Instruction[AND operand with ACC]
Control Line
Value
4-bit Binary Keyboard (Address Bus)
x
Write
0
Read
1
ACC to Data Bus
0
Load ACC
0
/~A_Only
1
/~Invert
0
Logic/~Arith
1
Instruction[ Store ACC to RAM]
Control Line
Value
4-bit Binary Keyboard (Address Bus)
X
Write
0
Read
1
ACC to Data Bus
1
Load ACC
0
/~A_Only
1
/~Invert
1
Logic/~Arith
1
Table 9
Instruction[ Not (operand) to ACC]
(1’s complement)
Control Line
Value
4-bit Binary Keyboard (Address Bus)
3
Write
1
Read
0
ACC to Data Bus
0
Load ACC
1
/~A_Only
1
/~Invert
0
Logic/~Arith
0
Instruction[ Negate(operand) to ACC]
(2’s complement)
Control Line
Value
4-bit Binary Keyboard (Address Bus)
3
Write
1
Read
0
ACC to Data Bus
0
Load ACC
1
/~A_Only
0
/~Invert
0
Logic/~Arith
1
Task 4-9: Build the Memory-Address-Generation Circuit
Include a picture of your Logisim memory address generation circuit here:
Task 4-10: Build the Controller Circuit
Include a picture of your Logisim controller circuit here:
Task 4-11: Build the Complete Microprocessor Circuit
Include a picture of your Logisim complete microprocessor circuit, with controller, here:
Task 4-12: Write and Execute a Simple Program for Your Microprocessor
Write the program given in your laboratory manual into the appropriate memory locations. Observe the operation of each step of your program (i.e. observe the values of the control lines and record whether data is being moved properly according to those control line settings). Did you get an 8 stored into the accumulator with you initial test?______
If not, what error(s) did you find during your debugging process?________________________________
_____________________________________________________________________________________
_____________________________________________________________________________________
Task 4-13: Add the ‘AND’, ‘Zero’, ‘Subtract’, and ‘Store ACC’ Instructions
Use Table 10and Table 11to enter your values into the microinstruction definition table for each of the four instructions asked for in the laboratory manual. Be sure to label the name of each and every instruction.
Table10
Instruction
Opcode
3
4
Pres. State
00
01
02
03
00
01
02
03
Description
Pin number
Next State Bits
1-0
Load IR
2
Write
3
Read
4
ACC to Data Bus
5
Load ACC
6
Load MAR
7
Use PC
8
/~A_only
9
/~Invert
10
Logic/~Arith
11
X
12
X
13
X
14
X
15
HEX equiv
Table11
Instruction
Opcode
5
6
Pres. State
00
01
02
03
00
01
02
03
Description
Pin number
Next State Bits
1-0
Load IR
2
Write
3
Read
4
ACC to Data Bus
5
Load ACC
6
Load MAR
7
Use PC
8
/~A_only
9
/~Invert
10
Logic/~Arith
11
X
12
X
13
X
14
X
15
HEX equiv
Test your instructions by writing and executing programs. Record at least four programs and the output of each program in tables like that of Table 12.
Table12
Program #0 ( Example: ADD = 3+5)
Address
Value
Operation (In English)
0
0
The ‘Load ACC’ Opcode
1
3
The number ‘3’ to be loaded into the Accumulator
2
1
The ‘Add to ACC’ Opcode
3
5
The number ‘5’ to be added to the Accumulator
4
2
The ‘Stop’ Opcode
What was the final output of your program? ___8__
Was the program successful? YES_
If not what error(s) did you find in your circuit?
Program # ( )
Address
Value
Operation (In English)
What was the final output of your program? _____
Was the program successful? Yes or No_
If not what error(s) did you find in your circuit?
Task 4-14: Invent Your Own Instruction (Extra Credit)
Fill in the following two tables for your invented instruction.
Instruction
Opcode
7
Pres. State
00
01
02
03
00
01
02
03
Description
Pin number
Next State Bits
1-0
Load IR
2
Write
3
Read
4
ACC to Data Bus
5
Load ACC
6
Load MAR
7
Use PC
8
/~A_only
9
/~Invert
10
Logic/~Arith
11
X
12
X
13
X
14
X
15
HEX equiv
Program # ( )
Address
Value
Operation (In English)
What was the final output of your program? _____
Was the program successful? Yes or No_
If not what error(s) did you find in your circuit?
Simulation Lab 4: Lab Report Grade Sheet
Instructor Assessment: Task Oriented
Grading Criteria
MaxPoints
Points Lost
Template
Neatness, Clarity, and Concision
2
Description of Assigned Tasks, Work Performed & Outcomes Met
Task 4-1: Build the Brainless Central Processing Unit
5
Task 4-2: Test and Control the Brainless Central Processing Unit
12
Task 4-3: Build the Addressing Logic
3
Task 4-4: Build a 4-Bit ROM Memory Cell
3
Task 4-5: Build 4-Bit Output Port
3
Task 4-6: Build the 4-Bit RAM Cell
3
Task 4-7: Build the Brainless Microprocessor
10
Task 4-8: Testing and Controlling the Brainless Microprocessor
14
Task 4-9: Build the Memory-Address-Generation Circuit
5
Task 4-10: Build the Controller Circuit
5
Task 4-11: Build the Complete Microprocessor Circuit
10
Task 4-12: Write and Execute a Simple Program for your Microprocessor
5
Task 4-13: Add the ‘AND’, ‘Zero’, ‘Subtract’, and ‘Store ACC’ Instructions
20
Task 4-14: Invent Your Own Instruction
(5 extra points)
Self-Assessment Worksheet (The content of the self-assessment worksheet will not be graded. Full credit is given for including the completed worksheet.)
(2 extra points)
Points Lost
Lab Score
Late Lab
Lab Score
Self-Assessment Worksheet
Put ‘X’s’ in the table below indicating how strongly you agree or disagree that the outcomes of the assigned tasks were achieved. Use ‘5’ to indicate that you ‘strongly agree’, ‘3’ to indicate that you are ‘neutral’, and ‘1’ to indicate that you ‘strongly disagree’. Use ‘NA’, ‘Not Applicable’, when the tasks you performed did not elicit this outcome. Credit will be given for including this worksheet with your lab report; however, your responses will not be graded. They are for your instructor’s information only.
Table 14: Self-Assessment of Outcomes for Simulation Lab 4: The Brainless Microprocessor
After completing the assigned tasks and report, I am able to:
5
4
3
2
1
NA
Build, debug and control a simulation of a central processing unit (CPU)
X
Build, debug and control a simulation of a ROM, RAM and an output port.
X
Build and debug a simulation of a microprocessor that is absent a controller.
X
Act as the controller for an elementary microprocessor.
X
Design a PROM-based controller for an elementary microprocessor.
X
Create an instruction set for an elementary microprocessor.
X
Use the language of your instruction set to create a program and enter it into memory.
X
Execute a program on your simulated microprocessor.
X
Write below any suggestions you have for improving this laboratory exercise so that the stated learning outcomes are achieved.
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